Assessing SRAM test coverage for sub-micron CMOS technologies
نویسندگان
چکیده
This paper proposes a realistic memory fault probability model which predicts the probabilities of memory fault classes for a given process technology. Physical defects in the memory array are classified into five functional fault classes, which are stuck-at, stuck-open, transition, coupling, and data retention faults. Finally, the memory fault coverages of the known memory test algorithms are evaluated based on their functional fault class coverages.
منابع مشابه
Ip-sram Architecture at Deep Submicron Cmos Technology – a Low Power Design
The growing demand for high density VLSI circuits the leakage current on the oxide thickness is becoming a major challenge in deep-sub-micron CMOS technology. In deep submicron technologies, leakage power becomes a key for a low power design due to its ever increasing proportion in chip‟s total power consumption. Motivated by emerging battery-operated application on one hand and shrinking techn...
متن کاملCharacterization of 9 T SRAM Cell at Various Process Corners at Deep Sub - micron Technology for Multimedia Applications
In the past decades CMOS IC technologies have been constantly scaled down and at present they aggressively entered in the nanometer regime. Amongst the wide-ranging variety of circuit applications, integrated memories especially the SRAM cell layout has been significantly reduced. As it is very well know the reduction of size of CMOS involves an increase in physical parameters variation, this i...
متن کاملAnalysis of Gate Leakage Current in IP 3 SRAM Bit - Cell under Temperature Variations in DSM Technology
In this paper, we present the temperature based simulation and analysis of gate leakage current for the proposed low-stress IP3 SRAM bit cell. In CMOS technologies, cache memory occupies a large die area and this may experience different temperatures. Under temperature variations, performance of the system may degrade. Therefore, in the IP3 SRAM cell, gate leakage has been analyzed under temper...
متن کاملStability Analysis of 6T SRAM Cell at 90nm Technology
SRAM is the most crucial part of memory designs and are imperative in many simple or compound applications that implicate system on chip (SoCs). Power dissipation and stability has now become the most essential area of concern in sub-micron SRAM cell design with continuous technology scaling according to Moore’s law. At latest, retrenchment of channel length MOSFET is directly proportional to t...
متن کاملLeakage Power Reduction in Deep Sub Micron Sram Design - a Review
Present day electronic industry faces the major problem of standby leakage current, as the processor speed increases, there is requirement of high speed cache memory. SRAM being mainly used for cache memory design, several low power techniques are being used for SRAM cell design. Full CMOS 6T SRAM cell is the most preferred choice for digital circuits. This paper reviews various leakage power t...
متن کامل